1. Technical Field
The present invention generally relates to a semiconductor integrated circuit, and more particularly, to a semiconductor device and a data output circuit therefor.
2. Related Art
In general, a semiconductor memory device performs an operation of reading data from a memory cell in response to an address and a read command received from a controller and performs an operation of writing data into a memory cell in response to an address and a write command received from the controller.
When a semiconductor memory device performs a read operation, a data signal outputted from a memory cell has potential of a very fine level. Accordingly, a logic level of this fine signal is determined by plural times of sense amplification circuits.
Meanwhile, a semiconductor memory device gradually requires lower power, and thus operating power for the semiconductor memory device is lowered. Accordingly, a high-performance data output device is necessary because a voltage level of a signal outputted from a memory cell becomes finer.
FIG. 1 shows a schematic construction of the data output circuit of a common semiconductor device. The data output circuit can include a bit line sense amplifier (BLSA) 101, a local sense amplifier (LSA) 103, an input/output sense amplifier (IOSA) 105, and an input/output buffer (I/O buffer) 107.
When a corresponding word line (not shown) is enabled in response to an address from a controller, data stored in a memory cell (not shown) is loaded onto a bit line pair BL and BLB. The BLSA 101 amplifies voltage corresponding to electric charges that are stored in the memory cell. The data amplified by the BLSA 101 is transferred to a pair of segment input/output lines SIO and SIOB when a column select signal YI is enabled.
The LSA 103 amplifies the data loaded onto the pair of segment I/O lines SIO and SIOB and supplies the amplified data to the IOSA 105 through a pair of local input/output lines LIO and LIOB. The IOSA 105 amplifies the received data again and sends the amplified data to a global input/output line GIO so that the data is externally outputted through the I/O buffer 107.
FIG. 2 shows the construction of a common LSA, and FIG. 3 is a timing diagram illustrating a data output method in a common semiconductor device.
Referring to FIG. 2, the LSA 103 can include an amplification unit 1031 for amplifying data loaded onto the pair of segment I/O lines SIO and SIOB and a switching unit 1033 for coupling or separating the pair of segment I/O lines SIO and SIOB and the pair of local I/O lines LIO and LIOB. FIG. 2 also illustrates, a terminal ground voltage Vss and a transistors T1 to T7.
The switching unit 1033 couples or separates the pair of segment I/O lines SIO and SIOB and the pair of local I/O lines LIO and LIOB in response to an I/O switch control signal IOSW. Particularly, the switching unit 1033 is configured to couple the pair of segment I/O lines SIO and SIOB and the pair of local I/O lines LIO and LIOB so that data is transmitted when a write operation is performed and configured to separate the pair of segment I/O lines SIO and SIOB and the pair of local I/O lines LIO and LIOB so that a differential amplification signal loaded onto the pair of segment I/O lines SIO and SIOB is transmitted to the pair of local I/O lines LIO and LIOB when a read operation is performed.
The data output method of the semiconductor device is described below with reference to FIGS. 1 to 3.
When a corresponding word line is enabled in response to an active command ACT (i.e., <ACT>), charge sharing is generated between a selected memory cell and the bit line BL, and thus a voltage difference is generated between the bit line BL and the bit line bar BLB. Furthermore, when the BLSA 101 is enabled, it amplifies the voltage difference between the pair of bit lines BL and BLB.
When a read command READ (i.e., <READ>) is enabled after RAS (i.e., row address strove/select) to CAS (i.e., column address strobe/select) delay (tRCD), the column select signal YI is enabled (i.e., YI(RD). After a lapse of a specific time, an LSA enable signal LSAEN is enabled.
When a read operation is performed, the I/O switch control signal IOSW remains off. When the LSA enable signal LSAEN is enabled, the transistors T3, T4, and T7 of the amplification unit 1031 are turned on. At this time, assuming that a logic state of data transmitted from the memory cell to the segment I/O line SIO is a high level (i.e., “H” Data) and a logic state of data transmitted from the memory cell to the segment I/O line bar SIOB is a low level (i.e., “L” Data), the transistor T5 of the amplification unit 1031 is turned on. Thus, a voltage level of the local I/O line bar LIOB is amplified to a low level and voltages levels of the pair of local I/O lines LIO and LIOB are amplified by a specific voltage difference.
As described above, the transistors T1 and T2 of the switching unit 1033 that are controlled in response to the I/O switch control signal IOSW are turned off when a read operation is performed, thus separating the pair of segment I/O lines SIO and SIOB and the pair of local I/O lines LIO and LIOB. Here, if the pair of segment I/O lines SIO and SIOB adjacent to each other has different data topologies, a coupling phenomenon is generated because the pair of segment I/O lines SIO and SIOB separated by the I/O switch control signal IOSW has a small potential load. In this case, a data read failure can be generated because the potentials of the pair of segment I/O lines SIO and SIOB are influenced by the coupling phenomenon.
Furthermore, as a power source voltage VDD rises, a failure probability increases because a coupling effect between the segment I/O lines is further increased.